Synopsys unveils AI and hyperscale data center chip solution for high bandwidth needs

Synopsys has delivered a dramatic increase in bandwidth and throughput for data-intensive AI workloads with the industry’s first complete 1.6T Ethernet IP solution. Hyperscale data centers, a backbone in the era of pervasive intelligence, require high-bandwidth, low-latency chips and interfaces to process petabytes of data quickly. Synopsys’ new 1.6T Ethernet IP solution enables design teams to create the industry’s fastest chips for AI and data center networking applications.

Synopsys is enabling hyperscale data center providers, and the ecosystem that serves them, to future-proof their infrastructure via their silicon roadmap, using the industry’s most extensive, interoperable, and proven IP portfolio:

“Massive artificial intelligence and machine learning workloads are accelerating the need for 1.6T Ethernet in data centers,” said Ram Periakaruppan, vice president and general manager, Network Test & Security Solutions, Keysight Technologies. “The combination of Synopsys’ new 1.6T Ethernet controllers and robust 224G Ethernet PHY IP and Keysight’s IxVerify pre-silicon test solution are essential to helping customers design the world’s fastest, most reliable system on a chip device.”

“Insatiable demand for high-speed data access is pushing hyperscale cloud providers to upgrade their networking infrastructure to maintain their competitive edge” said Keith Guetig, vice president of Product Management, Samtec. “With successful interoperability between this and many prior generations of Synopsys’ high-quality Ethernet solutions and Samtec’s high-speed FlyOver® cable assemblies, chip designers and system architects can reduce their design risk when developing the next generation of SoCs for cloud, AI, and 5G applications.”

“With growing demands from large language modeling, HPC simulation, and AI training in hyperscale data centers, network boundaries are crossing over the Terabits per second threshold,” said Peter Jones, chairman, Ethernet Alliance. “The availability of development tools capable of meeting these needs is critical to the success of next-generation Ethernet standards addressing this market.”

“The massive compute demands of hyperscale data centers require significantly faster Ethernet speeds to enable emerging AI workloads,” said John Koeter, senior vice president of marketing and strategy for IP, Synopsys. “Our complete IP solution for 1.6T Ethernet, pre-verified subsystems, successful ecosystem interoperability, and decades of expertise in developing and delivering the industry’s broadest interface IP portfolio allow designers to confidently integrate the necessary functionality into their SoCs with less risk.”

Synopsys’ comprehensive IP solution, including new 1.6T MAC and PCS Ethernet controllers, 224G Ethernet PHY IP, and verification IP, accelerates time to market for AI and HPC networking chips. The complete 1.6T Ethernet IP solution optimizes hyperscale data center energy efficiency by reducing interconnect power consumption by up to 50% compared to existing SoC implementations. 

The new multi-channel, multi-rate Synopsys 1.6T Ethernet MAC and PCS Controllers decrease area by 50% and reduce latency by 40% by implementing a patented Reed-Solomon Forward Error Correction architecture, while helping ensure reliable data for Ethernet rates from 10G to 1.6T. The silicon-proven 224G Ethernet PHY IP delivers robust link performance with exceptional signal integrity and seamless ecosystem interoperability for multiple channel lengths. The industry’s first Ethernet verification IP for up to 1.6T speeds, implemented in native SystemVerilog and Universal Verification Methodology, speeds time to first test.

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